Book description
Three-dimensional (3D) integration is identified as a possible avenue for continuous performance growth in integrated circuits (IC). Wafer level 3D IC can take several forms, and they usually include a stack of several thinned IC layers that are vertically bonded and interconnected by through silicon via TSV. This book presents contributions by key researchers in this field, covering motivations, technology platforms, applications, and other design issues.
Table of contents
- Cover
- Half Title
- Title
- Copyright
- Preface
- Contents
- Chapter 1 3D Integration Technology - Introduction and Overview
- Chapter 2 A Systems Perspective on 3D Integration: What is 3D? And What is 3D Good For?
- Chapter 3 Wafer Bonding Techniques
- Chapter 4 TSV Etching
- Chapter 5 TSV Filling
- Chapter 6 3D Technology Platform: Temporary Bonding and Release
- Chapter 7 3D Technology Platform: Wafer Thinning, Stress Relief, and Thin Wafer Handling
- Chapter 8 Advanced Die-to-Wafer 3D Integration Platform: Self-Assembly Technology
- Chapter 9 Advanced Direct Bond Technology
- Chapter 10 Surface Modification Bonding at Low Temperature for Three-Dimensional Hetero-Integration
- Chapter 11 Through Silicon Via Implementation in CMOS Image Sensor Product
- Chapter 12 A 300-mm Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through-Silicon Via and Hybrid Cu-Adhesive Bonding
- Chapter 13 Power Delivery in 3D IC Technology with a Stratum Having an Array of Monolithic DC-DC Point-of-Load (PoL) Converter Cells
- Chapter 14 Thermal-Aware 3D IC Designs
- Chapter 15 3D IC Design Automation Considering Dynamic Power and Thermal Integrity
- Chapter 16 Outlook
- Index
Product information
- Title: 3D Integration for VLSI Systems
- Author(s):
- Release date: April 2016
- Publisher(s): Jenny Stanford Publishing
- ISBN: 9781040000106
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