Chapter 13 POWER DELIVERY IN 3D IC TECHNOLOGY WITH A STRATUM HAVING AN ARRAY OF MONOLITHIC DC-DC POINT-OF-LOAD (POL) CONVERTER CELLS
Rensselaer Polytechnic Institute
Wafer-level three-dimensional (3D) integration offers the potential of enhanced performance and increased functionality, combined with the low manufacturing cost inherit from monolithic IC processing. This chapter addresses the problem of power delivery in microprocessors, application-specific ICs (ASICs) and system-on-a-chip (SoC) implementations, based upon a wafer-level 3D technology platform with arrays of monolithic DC-DC converter cells in one stratum providing power locally to the signal electronics strata. The chapter consists of five ...
Get 3D Integration for VLSI Systems now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.
