Unlike 8051 family, MCS-96 is designed around the Princeton architecture, allowing program and data
memory to share the same memory space. Total addressable memory space is 64K, which is divided in external
and internal parts, as shown in Fig. 26.8. e lower address space of the memory area is reserved for internal
on-chip RAM, which also accommodates SFRs and other CPU registers. Interrupts have their own vector
address, which is divided in two parts, upper and lower.
26.3.5 |Addressing Modes
MCS-96 off ers a rich instruction set and uses the following fi ve addressing modes.
(i) Direct
(ii) ...
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