A.4.13 | Instructions with Register Addressing Through the Accumulator
Opcode Bytes/Cycles Instruction Flags aff ected
25 2-1 ADD A, adr 8 C OV AC
26 1-1 ADD A, @R0 C OV AC
27 1-1 ADD A, @R1 C OV AC
24 2-1 ADD A, #dat 8 C OV AC
28 1-1 ADD A, R0 C OV AC
29 1-1 ADD A, R1 C OV AC
2A 1-1 ADD A, R2 C OV AC
2B 1-1 ADD A, R3 C OV AC
2C 1-1 ADD A, R4 C OV AC
2D 1-1 ADD A, R5 C OV AC
2E 1-1 ADD A, R6 C OV AC
2F 1-1 ADD A, R7 C OV AC
35 2-1 ADDC A, adr 8 C OV AC
36 1-1 ADDC A, @R0] ...
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