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A One-Semester Course in Modeling of VSLI Interconnections by Ashok Goel

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CHAPTER 3

Modeling of Interconnection Delays

The modern interconnection layout is an extremely high-density structure with millions of metallic lines running vertically and horizontally on various levels. The interconnection delays have been studied at length [172] and the delay models used in the industry have changed over time since the relative significance of the different interconnection parasitics (resistances, capacitances, and inductances) has changed over time. Until a few years ago, only interconnection capacitances were considered to be significant enough to contribute to the overall chip delay. With the advent of complex circuits, continuous scaling and the use of longer interconnection lines, interconnection resistance became an ...

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