book

ABCs of z/OS System Programming Volume 10

by Lydia Parziale, Patrick Oughton, Alvaro Salla

May 2018

Intermediate to advanced

164 pages

4h 32m

English

IBM Redbooks

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1.1 z/Architecture historical path1.2 Computer architecture overview1.3 Concept of a process1.4 System components1.4.1 System Assist Processor (SAP)1.4.2 Channels1.4.3 Dynamic Switch1.4.4 IBM Virtual Flash Memory (VFM)1.4.5 Pervasive encryption1.5 Processing units (PUs)1.6 Microcode Concepts1.7 z/Architecture Components1.8 PU Registers1.8.1 General purpose registers (GPR)1.8.2 Floating point registers1.9 Instruction set and its formats1.10 Program status word (PSW)1.10.1 PSW format1.11 Multiprocessing1.12 z/Architecture Data Formats1.12.1 Binary integers1.12.2 Decimal numbers1.12.3 Floating-point numbers1.12.4 EBCDIC data1.12.5 ASCII data1.12.6 Unicode1.12.7 UTF-81.13 IPL of a z/OS logical partition1.14 CPC memory addressing1.15 Addresses and address spaces1.16 Addressing mode1.16.1 AMODE1.16.2 RMODE1.17 Interrupts1.17.1 Reasons for interrupts1.17.2 Types of interrupts1.17.3 Interrupt processing1.18 Prefix Storage Area (PSA)1.19 Storage protection1.19.1 Storage key1.19.2 PSW key field1.19.3 Storage protection logic1.20 Virtual Storage initial concepts1.21 Segmenting a virtual address1.22 Dynamic address translation (DAT) (I)1.23 Dynamic Address Translation (DAT) (II)1.24 Translating large virtual address1.25 Page faults and page data sets1.26 A 64-bit Address Space1.27 Cross memory1.28 Access register mode (data spaces)1.29 z/Architecture time facilities1.30 Server Time Protocol (STP)1.31 Hardware Configuration Definition (HCD)1.32 Logical channel subsystem (LCSS)1.33 Start Subchannel (SSCH) instruction logic1.34 I/O Interrupt processing1.35 DASD controllers (aka DASD controller )1.36 Device number1.37 Subchannel and subchannel numbers1.38 Unit address and logical control unit1.39 I/O summary
2.1 Introducing the IBM z142.2 The z142.3 z14 Technical Highlights2.4 z14 System Design2.5 Processor unit (PU) instances2.6 z14 Hardware models2.7 z14 Sub-capacity models2.8 z14 frames, drawers, and I/O2.9 Processor Drawers2.10 Single Chip Module (SCM)2.11 Processor Unit (PU)2.12 Memory2.13 Power and Cooling2.13.1 Power2.13.2 Cooling2.14 Upgrades2.14.1 Permanent upgrades2.14.2 Temporary upgrades2.14.3 Concurrent upgrades2.14.4 Customer Initiated Upgrade facility2.14.5 Capacity Backup2.14.6 Capacity for Planned Events (CPE)
3.1 I/O channel overview3.1.1 I/O hardware infrastructure3.2 I/O connectivity features3.2.1 FICON EXPRESS3.2.2 zHyperLink Express3.2.3 Open Systems Adapter-Express3.2.4 HiperSockets3.3 Coupling links3.3.1 Coupling Express Long Reach (CE LR)3.3.2 Integrated Coupling Adapter: Short Reach (ICA SR)3.3.3 Host Channel Adapter3: Optical Long Reach (HCA3-O LR)3.3.4 Host Channel Adapter3: Optical (HCA3-O)3.3.5 Internal coupling3.4 Shared Memory Communications3.4.1 SMC-Remote Direct Memory Access (SMC-R)3.4.2 SMC-Direct Memory Access (SMC-D)3.5 Special-purpose feature support3.5.1 Crypto Express features3.5.2 Flash Express feature3.5.3 zEDC Express feature3.6 Channel Subsystem3.6.1 Multiple channel subsystems concept3.7 CSS configuration management3.8 Displaying channel types
4.1 Virtualization definitions and properties4.2 Virtualization concepts4.3 Virtualized physical resources4.4 Hypervisor types4.5 Hypervisor technologies (I)4.6 Hypervisor technologies (II)4.7 IBM Hypervisors on IBM Z family4.8 z/Virtual Machine (z/VM)4.9 z/VM options in HMC4.10 KVM for IBM Z and DPM4.10.1 Hypervisor terminology4.11 CPC in PR/SM mode4.12 Logical PU concept4.13 Shared and dedicated logical PU example4.14 PR/SM dispatching and shared CPs4.15 PR/SM Weights4.16 PR/SM capped versus uncapped4.17 Defined capacity or Soft capping4.18 Group Capacity
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