4.2. THE TECHNOLOGY STACK 49
1. Programming/Initialization. e weights h
i
; J
ij
are loaded onto qubit and coupler biases.
e qubits are placed in superposition according to H
I
which is scaled by A.0/. Program-
ming raises the chip temperature, so this step also includes a wait time for the chip to cool
back down to operating temperature. As shown in Table 4.1, initialization dominates the
computation time but this cost has decreased with succeeding chip models.
2. Anneal. A transition takes place whereby the forces on the qubits change according to
the path functions in Figure 4.3. Anneal time t
f
can be set by the user: Table 4.1 shows
minimum possible settings for V5 and V6.
3. Readout. e transition ends. e qubits now have classical spin states according to H
IM
,
which is scaled by B.1/. Qubit values are read to yield the solution S. is step also includes
a short wait time for the chip to cool down for resampling.
4. Resampling. Since the chip operates in an open system, there is always a positive (some-
times significant) probability that the computation does not finish in ground state. Given
the relatively high initialization times it is cost-effective to repeat the anneal-readout cy-
cle many times, typically k D 1,000 or k D 10,000. us a given chip requires time
T
k
D T
p
C k.T
a
C T
r
/ to return a sample of k solutions to one instance. e last column
in Table 4.1 shows total time to sample k D 1,000 solutions.
Table 4.1: Computation times for a Model One C
4
, and two Model Two C
8
chips in the Vesuvius
series. e second column shows the number of working qubits on the chip. e next three columns
show times for initialization, anneal, and readout. e last column shows total time to sample k D
1,000 solutions for one instance (Sources: Bain et al. [5] (One), McGeoch and Wang [70] (Two)).
Chip Qubits T
p
T
a
T
r
T
1000
One 102 270ms 1ms 1.5ms 2770ms
Two V5 439 201ms 20s .29ms 491ms
Two V6 502 36ms 20s .13ms 196ms
4.2 THE TECHNOLOGY STACK
is section gives a quick overview of the D-Wave technology stack. ree layers are highlighted
here:
Qubits. Section 4.2.1 describes the superconducting flux qubits used to represent quantum
state.
Connection topology. Section 4.2.2 discusses features of the Chimera structure.

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