8Embedded Silicon Fan‐Out (eSiFO®) Technology for Wafer‐Level System Integration

Daquan Yu

Huatian Technology (Kunshan) Electronics Co.,Ltd., Economic & Technical Development Zone, Kunshan, Jiangsu, China

8.1 Technology Description

The demand for miniaturized package size, higher performance and integration density, lower power consumption, and lower manufacturing cost drives the development of various new packaging technologies. Among those new packaging technologies, the fan‐out wafer‐level package (FO‐WLP) has emerged as a successful technology in providing the solution to fulfill the abovementioned requirements. FO‐WLP has also become a key‐enabling technology for multi‐chip and 3D system integration [1]. As one type of FO‐WLP, embedded silicon fan‐out (eSiFO) technology, in which silicon instead of molding compound was used as the fan‐out area, was proposed in 2015 [2]. It is a chip‐first and face‐up process, eliminating molding, temporary bonding, and debonding process and has been in volume production not only for single‐die package but also for multi‐die system‐in‐package (SiP) applications.

8.2 Basic Package Construction

Figure 8.1 shows the structure of an eSiFO package. In the package, known good die (KGD) were embedded in a silicon carrier, and the microgaps between the die and silicon carrier were filled by polymer. The die and silicon carrier reconstruct a surface for the routing of redistribution layers (RDL) and fabrication of solder balls. The main difference ...

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