Advances in Embedded and Fan-Out Wafer Level Packaging Technologies

16The Role of Pick and Place in Fan‐Out Wafer‐Level Packaging

Hugo Pristauz, Alastair Attard, and Harald Meixner

BESI, Austria

16.1 Introduction

Pick and place (P&P) is a crucial subprocess for fan‐out and embedded wafer‐ and panel‐level packaging, as it is an essential contribution to the package cost of ownership. It also has a significant influence on the yield as P&P is challenged by high placement accuracy requirements over a large working area and by the absence of local alignment marks in several fan‐out technologies. Stable die P&P accuracy plays a key role for product feasibility [1]. To introduce some important P&P capabilities, a set of well‐documented fan‐out and embedded packaging processes can be consulted, like embedded wafer‐level ball grid array (eWLB) [2, 3], redistributed chip package (RCP) [4], wafer‐level integrated fan‐out (InFO) [5], M‐Series (a fully molded fan‐out packaging technology) [6], silicon wafer integrated fan‐out technology (SWIFT) [7], silicon‐less integrated module (SLIM) [8], and embedded multi‐die interconnect bridge (EMIB) [9]. This set of processes has no claim on completeness (some more can be found in [10]), but is representative to highlight important P&P requirements for fan‐out and embedded wafer‐ and panel‐level packaging processes.

Early deployed fan‐out packaging processes like eWLB and RCP require die attach with the active side down (face‐down) onto a sticky carrier [2–4]. Since the die is placed before processing of the redistribution ...