Advances in Embedded and Fan-Out Wafer Level Packaging Technologies

23Embedded Multi‐die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect

Ravi Mahajan, Robert Sankman, Kemal Aygun, Zhiguo Qian, Ashish Dhall, Jonathan Rosch, Debendra Mallik, and Islam Salama

Intel Corporation, Chandler, AZ, USA

23.1 Introduction

The need for high memory bandwidth between the central processing unit (CPU) and dynamic random‐access memory (DRAM) has led to increased focus on high bandwidth on‐package links in recent years [1–3]. The performance of the input/output (I/O) subsystem (or link) that delivers this bandwidth is measured by its power consumption and bandwidth, both of which depend on the transceiver circuits and the I/O channel. It should be noted that link performance is also affected by latency; however this aspect is not covered here since it requires a deeper discussion of link architectures that is beyond the scope of the present chapter. The peak bandwidth of an I/O link is the product of the number of data lanes and the data rate, two factors that can be scaled to enable bandwidth scaling:

1. Increasing the number of data lanes creates the so‐called wide and slow I/O links where the density of all the components in the physical channel, i.e. the I/O circuits, bumps, and wires, is scaled. This allows use of a lower signaling frequency in the I/O link and hence improved power efficiency due to reduction in circuit complexity and/or voltage scaling [4]. The main challenge for enabling wide and slow links ...