Analog VLSI Circuits for the Perception of Visual Motion

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Smooth Optical Flow Chip

The smooth optical flow chip is the silicon realization of the optical flow network. It contains a homogeneous array of optical flow units. Because of the modular layout, the array size and thus the resolution of the optical flow estimate can be almost arbitrary. This chapter carefully characterizes the smooth optical flow chip and shows how it behaves under real-world visual conditions. Two versions of the smooth optical flow chip have been produced so far which are essentially identical in the layout of the single optical flow unit. They only differ in their array sizes where the smaller chip has 10 × 10 and the larger 30 × 30 units, respectively. These are the effective array sizes, that is the number of functional optical flow units. On each side of the array, there is an additional row of photoreceptor circuits necessary for computing the spatial brightness gradients of the edge units. Exact specifications of the two circuits and the process technology are listed in Appendix D.

In addition to the optical flow array, the chip also includes peripheral circuitry for power supply and biasing of the circuits, and to read out the signals of the optical flow network. There is no possibility to have a simultaneous read-out of all units in the optical flow array because that would require an unfeasible number of wires. Instead, a scanner circuit permits sequentially addressing of each unit such that they can be read out one at a time [Mead and Delbrück 1991]. ...