O'Reilly logo

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

Architecture-Aware Optimization Strategies in Real-time Image Processing

Book Description

In the field of image processing, many applications require real-time execution, particularly those in the domains of medicine, robotics and transmission, to name but a few. Recent technological developments have allowed for the integration of more complex algorithms with large data volume into embedded systems, in turn producing a series of new sophisticated electronic architectures at affordable prices.  This book performs an in-depth survey on this topic. It is primarily written for those who are familiar with the basics of image processing and want to implement the target processing design using different electronic platforms for computing acceleration.  The authors present techniques and approaches, step by step, through illustrative examples. This book is also suitable for electronics/embedded systems engineers who want to consider image processing applications as sufficient imaging algorithm details are given to facilitate their understanding.

Table of Contents

  1. Cover
  2. Title
  3. Copyright
  4. Preface
  5. 1 Introduction of Real-time Image Processing
    1. 1.1. General image processing presentation
    2. 1.2. Real-time image processing
  6. 2 Hardware Architectures for Real-time Processing
    1. 2.1. History of image processing hardware platforms
    2. 2.2. General-purpose processors
    3. 2.3. Digital signal processors
    4. 2.4. Graphics processing units
    5. 2.5. Field programmable gate arrays
    6. 2.6. SW/HW codesign of real-time image processing
    7. 2.7. Image processing development environment description
    8. 2.8. Comparison and discussion
  7. 3 Rapid Prototyping of Parallel Reconfigurable Instruction Set Processor for Efficient Real-Time Image Processing
    1. 3.1. Context and problematic
    2. 3.2. Related works
    3. 3.3. Design exploration framework
    4. 3.4. Case study: RISP conception and synthesis for spatial transforms
    5. 3.5. Hardware implementation of spatial transforms on an FPGA-based platform
    6. 3.6. Discussion and conclusion
  8. 4 Exploration of High-Level Synthesis Technique
    1. 4.1. Introduction of HLS technique
    2. 4.2. Vivado_HLS process presentation
    3. 4.3. Case of HLS application: FPGA implementation of an improved skin lesion assessment method
    4. 4.4. Discussion
  9. 5 CDMS4HLS: A Novel Source-To-Source Compilation Strategy for HLS-Based FPGA Design
    1. 5.1. S2S compiler-based HLS design framework
    2. 5.2. CDMS4HLS compilation process description
    3. 5.3. CDMS4HLS compilation process evaluation
    4. 5.4. Discussion
  10. 6 Embedded Implementation of VHR Satellite Image Segmentation
    1. 6.1. LSM description
    2. 6.2. Implementation and optimization presentation
    3. 6.3. Experiment evaluation
    4. 6.4. Discussion and conclusion
  11. 7 Real-time Image Processing with Very High-level Synthesis
    1. 7.1. VHLS motivation
    2. 7.2. Image processing from Matlab to FPGA-RTL
    3. 7.3. VHLS process presentation
    4. 7.4. VHLS implementation issues
    5. 7.5. Future work for real-time image processing with VHLS
  12. Bibliography
  13. Index
  14. End User License Agreement