4.6. SYSTEM OPERATION AND PROGRAMMING IN C 87
}
//*************************************************************************
//USART_transmit: transmits single byte of data
//*************************************************************************
void USART_transmit(unsigned char data)
{
while((UCSRA & 0x20)==0x00) //wait for UDRE flag
{
;
}
UDR = data; //load data to UDR for transmission
}
//*************************************************************************
//USART_receive: receives single byte of data
//*************************************************************************
unsigned char USART_receive(void)
{
while((UCSRA & 0x80)==0x00) //wait for RXC flag
{
;
}
data = UDR; //retrieve data from UDR
return data;
}
//*************************************************************************
4.6.1 SERIAL PERIPHERAL INTERFACE—SPI
The ATmega328 Serial Peripheral Interface or SPI also provides for two-way serial communication
between a transmitter and a receiver. In the SPI system, the transmitter and receiver share a common
clock source. This requires an additional clock line between the transmitter and receiver but allows
for higher data transmission rates as compared to the USART. The SPI system allows for fast
and efficient data exchange between microcontrollers or peripheral devices. There are many SPI
compatible external systems available to extend the features of the microcontroller. For example, a
88 4. SERIAL COMMUNICATION SUBSYSTEM
liquid crystal display or a digital-to-analog converter could be added to the microcontroller using
the SPI system.
4.6.1.1 SPI Operation
The SPI may be viewed as a synchronous 16-bit shift register with an 8-bit half residing in the
transmitter and the other 8-bit half residing in the receiver as shown in Figure 4.6. The transmitter
is designated the master since it is providing the synchronizing clock source between the transmitter
and the receiver. The receiver is designated as the slave. A slave is chosen for reception by taking its
Slave Select (
SS) line low. When the SS line is taken low, the slave’s shifting capability is enabled.
SPI transmission is initiated by loading a data byte into the master configured SPI Data
Register (SPDR). At that time, the SPI clock generator provides clock pulses to the master and also
to the slave via the SCK pin. A single bit is shifted out of the master designated shift register on
the Master Out Slave In (MOSI) microcontroller pin on every SCK pulse. The data is received at
the MOSI pin of the slave designated device. At the same time, a single bit is shifted out of the
Master In Slave Out (MISO) pin of the slave device and into the MISO pin of the master device.
After eight master SCK clock pulses, a byte of data has been exchanged between the master and
slave designated SPI devices. Completion of data transmission in the master and data reception in
the slave is signaled by the SPI Interrupt Flag (SPIF) in both devices. The SPIF flag is located in
the SPI Status Register (SPSR) of each device. At that time, another data byte may be transmitted.
SPI Data Register (SDR)
MSB LSB
SCK
Master Device
Slave Device
MOSI
(PB5)
MOSI
(PB5)
MISO
(PB6)
MISO
(PB6)
SPI Clock Generator
system
clock
SPI Data Register (SDR)
MSB LSB
SCK
SCK
(PB7)
SCK
(PB7)
SS
(PB4)
SS
(PB4)
shift
enable
SPI Status Register (SPSR)
SPI Control Register (SPCR)
Figure 4.6: SPI Overview.
4.6. SYSTEM OPERATION AND PROGRAMMING IN C 89
4.6.1.2 Registers
The registers for the SPI system are provided in Figure 4.7. We will discuss each one in turn.
70
70
SPI Status Register - SPSR
SPIF WCOL SPI2X--- --- --- --- ---
SPI Control Register - SPCR
SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0
70
SPI Data Register - SPDR
MSB
LSB
Figure 4.7: SPI Registers
SPI Control Register (SPCR) The SPI Control Register (SPCR) contains the “on/off ” switch for
the SPI system. It also provides the flexibility for the SPI to be connected to a wide variety of devices
with different data formats. It is important that both the SPI master and slave devices be configured
for compatible data formats for proper data transmission. The SPCR contains the following bits:
SPI Enable (SPE) is the on/off ” switch for the SPI system. A logic one turns the system on
and logic zero turns it off.
Data Order (DORD) allows the direction of shift from master to slave to be controlled. When
the DORD bit is set to one, the least significant bit (LSB) of the SPI Data Register (SPDR)
is transmitted first. When the DORD bit is set to zero the Most Significant Bit (MSB) of the
SPDR is transmitted first.
The Master/Slave Select (MSTR) bit determines if the SPI system will serve as a master (logic
one) or slave (logic zero).
The Clock Polarity (CPOL) bit allows determines the idle condition of the SCK pin. When
CPOL is one, SCK will idle logic high; whereas, when CPOL is zero, SCK will idle logic
zero.
The Clock Phase (CPHA) determines if the data bit will be sampled on the leading (0) or
trailing (1) edge of the SCK.

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