56 3. ANALOG-TO-DIGITAL CONVERSION
shows the overall architecture of this converter. Similar to the converter based on the integration
principle, the disadvantage of this type of converter is the varying conversion time.
3.3.4 PARALLEL CONVERSION
The last technique allows the quickest conversion time among the techniques we discussed. A
parallel converter uses a large number of comparators and circuitry to simultaneously measure the
input signal and convert it to a digital value. The obvious disadvantage of this technique is the cost
involved in building the circuitry. Figure 3.12(d) shows the architecture of the converter.
3.4 THE ATMEL ATMEGA164 ADC SYSTEM
The Atmel ATmega164 [6] microcontroller is equipped with a flexible and powerful ADC system.
It has the following features:
10-bit resolution,
±2 LSB absolute accuracy,
13 ADC clock cycle conversion time,
8 multiplexed single-ended input channels,
selectable right or left result justification, and
0 to Vcc ADC input voltage range.
L et us discuss each feature in turn. The first feature of discussion is “10-bit resolution.”
Resolution is defined as:
resolution = (V
RH
V
RL
)/2
b
.
V
RH
and V
RL
are the ADC high and low reference voltages, whereas b is the number of bits
available for conversion. For the ATmega164 with reference voltages of 5 VDC, 0 VDC, and 10
bits available for conversion, resolution is 4.88 mV. Absolute accuracy specified as ±2 LSB is then
±9.76 mV at this resolution.
It requires 13 analog-to-digital c lock cycles to perform an ADC conversion.The ADC system
may be run at a slower clock frequency (50 to 200 kHz) than the main microcontroller c lock source.
The main microcontroller cloc k is divided down using the ADC Prescaler Select (ADPS[2:0]) bits
in the ADC Control and Status Register A (ADCSRA).
The ADC is equipped with a single successive approximation converter. Onl y a single ADC
channel may be converted at a given time. The input of the ADC is equipped with an eight-input
analog multiplexer.The analog input for conversion is selected using the MUX[4:0] bits in the ADC
Multiplexer Selection Register (ADMUX).
The 10-bit result from the conversion process is placed in the ADC Data Registers, ADCH
and ADCL. These two registers provide 16 bits for the 10-bit result. The result may be left justified
3.4. THE ATMEL ATMEGA164 ADC SYSTEM 57
Figure 3.13: Atmel AVR ATmega164 ADC block diagram. Figure used with permission of Atmel.

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