5.7. TIMER 1 93
Figure 5.10: Timer 1 block diagram. (Figure used with Permission, Atmel,Inc.)
occurs, the value of the Timer/Counter 1 (TCNT1) register is captured and stored in the Input
Capture Register 1 (ICR1).
5.7.1 TIMER 1 REGISTERS
The complement of registers supporting Timer 1 are shown in Figure 5.11. Each register will be
discussed in turn.
TCCR1A and TCCR1B registers
The TCCR1 register bits are used to:
94 5. TIMING SUBSYSTEM
Timer/Counter 1 Control Register A (TCCR1A)
70
COM1A1 COM1A0 COM1B1 COM1B0 WGM11 WGM10
--- ---
70
Timer/Counter 1 Control Register B (TCCR1B)
ICNC1 ICES1 --- WGM13 WGM12 CS12 CS11 CS10
70
Timer/Counter Interrupt Mask Register 1 (TIMSK1)
ICIE1
OCIE1AOCIE1B
TOIE1
70
Timer/Counter 1 Interrupt Flag REgister (TIFR1)
ICF1 OCF1AOCF1B TOV1---
--- ------
70
Input Capture Register 1 (ICR1H/ICR1L)
15
8
--- --- --- ---
70
Timer Counter1 (TCNT1H/TCNT1L)
15
8
70
Output Compare Register 1 A (OCR1AH/OCR1AL)
15
8
70
Output Compare Register 1 B (OCR1BH/OCR1BL)
15
8
Timer/Counter 1 Control Register C (TCCR1C)
70
--- --- --- ------ ---FOC1A FOC1B
Figure 5.11: Timer 1 registers.
5.7. TIMER 1 95
Select the operational mode of Timer 1 using the Waveform Mode Generation (WGM1[3:0])
bits,
Determine the operation of the timer within a specific mode with the Compare Match Output
Mode (Channel A: COM1A[1:0] and Channel B: COM1B[1:0]) bits, and
Select the source of the Timer 1 clock using Clock Select (CS1[2:0]) bits.
The bit settings for the TCCR1A and TCCR1B registers are summarized in Figure 5.12.
Timer/Counter Register 1 (TCNT1H/TCNT1L)
The TCNT1 is the 16-bit counter for Timer 1.
Output Compare Register 1 (OCR1AH/OCR1AL)
The OCR1A register holds a user-defined 16-bit value that is continuously compared to the TCNT1
register when Channel A is used.
OCR1BH/OCR1BL
The OCR1B register holds a user-defined 16-bit value that is continuously compared to the TCNT1
register when Channel B is used.
Input Capture Register 1 (ICR1H/ICR1L)
ICR1 is a 16-bit register used to capture the value of the TCNT1 register when a desired edge on
ICP1 pin has occurred.
Timer/Counter Interrupt Mask Register 1 (TIMSK1)
Timer 1 uses the Timer/Counter 1 Output Compare Match Interrupt Enable (OCIE1A/1B) bits,
the Timer/Counter 1 Overflow Interrupt Enable (TOIE1) bit, and the Timer/Counter 1 Input
Capture Interrupt Enable (IC1E1) bit.When the OCIE1A/B bit and the I-bit in the Status Register
are both set to one, the Timer/Counter 1 Compare Match interrupt is enabled. When the OIE1 bit
and the I-bit in the Status Register are both set to one, the Timer/Counter 1 Overflow interrupt
is enabled. When the IC1E1 bit and the I-bit in the Status Register are both set to one, the
Timer/Counter 1 Input Capture interrupt is enabled.
Timer/Counter Interrupt Flag Register (TIFR1)
Timer 1 uses the Output Compare Flag 1 A/B (OCF1A/B) which sets for an output compare
A/B match. Timer 1 also uses the Timer/Counter 1 Overflow Flag (TOV1) which sets when
Timer/Counter 1 overflows. Timer Channel 1 also uses the Timer/Counter 1 Input Capture Flag
(ICF1) which sets for an input capture event.
96 5. TIMING SUBSYSTEM
Waveform Generation Mode
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
WGM[13:12:11:10]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Mode
Normal
PWM, Phase Correct, 8-bit
PWM, Phase Correct, 9-bit
PWM, Phase Correct, 10-bit
CTC
Fast PWM, 8-bit
Fast PWM, 9-bit
Fast PWM, 10-bit
PWM, Phase & Freq Correct
PWM, Phase & Freq Correct
PWM, Phase Correct
PWM, Phase Correct
CTC
Reserved
Fast PWM
Fast PWM
Clock Select
CS0[2:0] Clock Source
000 None
001 clk
I/0
010 clk
I/0
/8
011 clk
I/0
/64
100 clk
I/0
/8clk
I/0
/256
101 clk
I/0
/8clk
I/0
/1024
110 External clock on T0 (falling edge trigger)
111 External clock on T1 (rising edge trigger)
COMx[1:0]
00
01
10
11
Description
Normal, OC0 disconnected
WGM1[3:0] = 9 or 14: toggle OCnA
on compare match, OCnB discon-
nected
WGM1[3:0]= other settings,
OC1A/1B disconnected
Clear OC0 on compare match
when up-counting. Set OC0
on compare match when
down counting
Set OC0 on compare match
when up-counting. Clear OC0
on compare match when
down counting.
PWM, Phase Correct, Phase & Freq Correct
COMx[1:0]
00
01
10
11
Normal, CTC
Description
Normal, OC1A/1B disconnected
Toggle OC1A/1B on compare match
Clear OC1A/1B on compare match
Set OC1A/1B on compare match
COMx[1:0]
00
01
10
11
Fast PWM
Description
Normal, OC1A/1B disconnected
WGM1[3:0] = 15, toggle OC1A on
compare match OC1B disconnected
WGM1[3:0] = other settings,
OC1A/1B disconnected
Clear OC1A/1B on compare match,
set OC1A/1B at TOP
Set OC1A/1B on compare match,
clear OC1A/1B at TOP
Timer/Counter 1 Control Register A (TCCR1A)
70
COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10
70
Timer/Counter 1 Control Register B (TCCR1B)
ICNC1 ICES1 WGM13 WGM12 CS12 CS11 CS10
Figure 5.12: TCCR1A and TCCR1B registers.

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