Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP Routers

CHAPTER 3

INPUT-BUFFERED SWITCHES

When high-speed packet switches were constructed for the first time, they used either internal shared buffer or input buffer and suffered the problem of throughput limitation. As a result, most early-date research has focused on the output buffering architecture. Since the initial demand of switch capacity is at the range of a few to 10–20 Gbit/s, output buffered switches seem to be a good choice for their high delay throughput performance and memory utilization (for shared-memory switches). In the first few years of deploying ATM switches, output-buffered switches (including shared-memory switches) dominated the market. However, as the demand for large-capacity switches increases rapidly (either line rates or the switch port number increases), the speed requirement for the memory must increase accordingly. This limits the capacity of output-buffered switches. Therefore, in order to build larger-scale and higher-speed switches, people have focused on input-buffered or combined input–output-buffered switches with advanced scheduling and routing techniques, which are the main subjects of this chapter.

Input-buffered switches have two problems: (1) throughput limitation due to the head-of-line (HOL) blocking and (2) the need of arbitrating cells due ...