Book description
This handbook provides ready access to all of the major concepts, techniques, problems, and solutions in the emerging field of pseudorandom pattern testing. Until now, the literature in this area has been widely scattered, and published work, written by professionals in several disciplines, has treated notation and mathematics in ways that vary from source to source. This book opens with a clear description of the shortcomings of conventional testing as applied to complex digital circuits, revewing by comparison the principles of design for testability of more advanced digital technology. Offers in-depth discussions of test sequence generation and response data compression, including pseudorandom sequence generators; the mathematics of shift-register sequences and their potential for built-in testing. Also details random and memory testing and the problems of assessing the efficiency of such tests, and the limitations and practical concerns of built-in testing.
Table of contents
- Cover Page
- Title Page
- Copyright
- Dedication
- Preface
- Contents
-
1: Digital Testing and the Need for Testable Designs
- 1.1 THE EVOLUTION OF TEST TECHNOLOGY
- 1.2 FAULT MODELS
- 1.3 STRUCTURAL AND FUNCTIONAL TESTING
- 1.4 ON-LINE VERSUS OFF-LINE TESTING
- 1.5 THE RELATIONSHIP BETWEEN DESIGN AND TEST
- 1.6 THE RELATIONSHIP BETWEEN PACKAGING LEVELS AND TEST
- 1.7 THE RELATIONSHIP BETWEEN DENSITY AND TEST
- 1.8 TEST GENERATION TECHNIQUES FOR COMBINATIONAL AND SEQUENTIAL CIRCUITS
- 1.9 TEST GENERATION COSTS AND PROJECTIONS
- 1.10 BUILT-IN TEST AS THE SOLUTION TO TESTING VLSI DESIGNS
- 2: Introduction to Testable Design
- 3: Pseudorandom Sequence Generators
- 4: Test Response Compression Techniques
-
5: Shift Register Polynomial Division
- 5.1 POLYNOMIAL REPRESENTATION OF BINARY DATA
- 5.2 IMPLEMENTATION OF A CRC GENERATOR
- 5.3 ERROR POLYNOMIALS
- 5.4 ALTERNATIVE LFSR IMPLEMENTATION OF POLYNOMIAL DIVISION
- 5.5 VARIOUS FEEDBACK STRUCTURES
- 5.6 ALTERNATIVE DESCRIPTIONS OF SIGNATURE REGISTERS
- 5.7 MULTIPLE-INPUT SIGNATURE REGISTERS
- 5.8 MASKING IN MULTIPLE-INPUT SIGNATURE REGISTERS
- 5.9 MISR AS A SINGLE-INPUT SIGNATURE ANALYZER
- 5.10 RECIPROCAL POLYNOMIALS
- 5.11 WHAT POLYNOMIAL SHOULD BE USED FOR SIGNATURE ANALYSIS?
- 5.12 IMPROVING THE EFFECTIVENESS OF SIGNATURE ANALYSIS
- 5.13 SEQUENTIAL CIRCUITS
- 5.14 GENERATION OF THE GOOD MACHINE SIGNATURE
- 5.15 SUMMARY
- 6: Special Purpose Shift-Register Circuits
-
7: Random Pattern Built-in Test
- 7.1 RANDOM PATTERN TEST
- 7.2 ERROR LATENCY FOR COMBINATIONAL AND SEQUENTIAL CIRCUITS
- 7.3 SIGNAL PROBABILITY COMPUTATION
- 7.4 DETECTION PROBABILITY CALCULATION
- 7.5 THE RANDOM PATTERN TEST LENGTH
- 7.6 WEIGHTED RANDOM PATTERNS
- 7.7 LOGIC MODIFICATION
- 7.8 RANDOM PATTERN TESTABILITY IN STRUCTURED DESIGNS
- 7.9 OTHER RANDOM PATTERN TESTABILITY EVALUATION METHODS
- 7.10 RANDOM PATTERN TESTING OF RANDOM ACCESS MEMORIES
- 7.11 FAULT PROPAGATION THROUGH RANDOM ACCESS MEMORIES
- 7.12 RANDOM PATTERN TESTABILITY OF DELAY FAULTS
- 7.13 TESTING FOR INTERMITTENT FAULTS
- 8: Built-in Test Structures
- 9: Limitations of and Other Concerns Random Pattern Testing
- 10: Test System Requirements for Built-in Test
- APPENDIX: A Primitive Polynomial for Every Degree through 300
- References
- Index
Product information
- Title: Built In Test for VLSI: Pseudorandom Techniques
- Author(s):
- Release date: October 1987
- Publisher(s): Wiley-Interscience
- ISBN: 9780471624639
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