Built In Test for VLSI: Pseudorandom Techniques

Contents

1 Digitai Testing and the Need for Testable Design

1.1 The Evolution of Test Technology

1.2 Fault Models

1.3 Structural and Functional Testing

1.4 On-Line versus Off-Line Testing

1.5 The Relationship between Design and Test

1.6 The Relationship between Packaging Levels and Test

1.7 The Relationship between Density and Test

1.8 Test Generation Techniques for Combinational and Sequential Circuits

1.9 Test Generation Costs and Projections

1.10 Built-in Test as the Solution to Testing VLSI Designs

2 Introduction to Testable Design

2.1 Ad Hoc Design Techniques

2.1.1 Logic Partitioning

2.1.2 Clock Isolation

2.1.3 Memory Array Isolation

2.1.4 Test Points

2.1.5 Bus Access

2.2 Structured Design Techniques

2.2.1 Level-Sensitive Scan Design

2.2.2 Random-Access Scan

2.2.3 Scan Path

2.2.4 Scan/Set Logic

2.3 Built-ln Test

2.3.1 Response Analysis

2.3.2 Off-Line Built-in Test Methodologies

2.4 Testability Measures

2.4.1 The Stephenson-Grason Testability Measure

2.4.2 SCOAP

2.4.3 VICTOR

2.4.4 Limitations of Testability Measures

3 Pseudorandom Sequence Generators

3.1 Shift-Register Implementation of a Pseudorandom Sequence

3.2 Analysis of Shift-Register Sequences

3.3 Periodicity of Shift-Register Sequences

3.4 Primitive Polynomials

3.5 Characteristics of Maximum-Length Linear Shift-Register ...