
Communication Buses for SoC Architectures 45
FIGURE 2.12
Typical IBM CoreConnect architecture with different buses and interconnect
bridges.
2.4.5 Coreconnect Tools
2.4.5.1 Design Toolkits
Design toolkits are available for each of the on-chip buses. These toolkits
contain master, slave and arbiter Bus Functional Models (BFM). They also
provide a Bus Functional Compiler used to translate test cases written in a
bus functional language into simulator commands executable by the master
and slave models. The toolkits are available in Very-High-Speed Integrated
Circuits (VHSIC), Hardware Description Language (VHDL), and Verilog such
that they can be used in any ...