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Communication Architectures for Systems-on-Chip
book

Communication Architectures for Systems-on-Chip

by José L. Ayala
September 2018
Intermediate to advanced content levelIntermediate to advanced
449 pages
13h 16m
English
CRC Press
Content preview from Communication Architectures for Systems-on-Chip
108 Communication Architectures for SoC
FIGURE 3.16
Element Interconnect Bus Architecture.
local or main memory or I/O. However, the bus access semantics and the ring
topology can lead to a worst-case throughput of 50% with adversarial traffic
patterns.
The access to rings (i.e., resource allocation) is controlled for the ring ar-
biter by priority policy. The highest priority is given to the memory controller
so requestors will not be stalled on read data. Other elements on the EIB have
equal priority and are served in a round-robin manner.
The routing in the EIB consists in the choice between left or right on
each of the four unidirectional rings. The ...
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Publisher Resources

ISBN: 9781439841716