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Communication Architectures for Systems-on-Chip
book

Communication Architectures for Systems-on-Chip

by José L. Ayala
September 2018
Intermediate to advanced content levelIntermediate to advanced
449 pages
13h 16m
English
CRC Press
Content preview from Communication Architectures for Systems-on-Chip
NoC Architectures 113
tiled core clusters with high-speed I/Os on the periphery. Each core has a
private 256 KB L2 cache (12 MB total on-die) and is optimized to support
a message-passing-programming model whereby cores communicate through
shared memory. A 16 KB message-passing buffer (MPB) is present in every
tile, giving a total of 384 KB on-die shared memory, for increased performance.
Memory accesses are distributed over four on-die DDR3 controllers for an
aggregate peak memory bandwidth of 21 GB/s. The die area is 567 mm
2
,
implemented in 45 nm.
FIGURE 3.19
The Single-Chip Cloud Computer Architecture.
The design is organized in a 6×4 2D-array of tiles ...
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Publisher Resources

ISBN: 9781439841716