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Communication Architectures for Systems-on-Chip
book

Communication Architectures for Systems-on-Chip

by José L. Ayala
September 2018
Intermediate to advanced content levelIntermediate to advanced
449 pages
13h 16m
English
CRC Press
Content preview from Communication Architectures for Systems-on-Chip
142 Communication Architectures for SoC
used to send packets to a destination only if enough buffering is available at
the receiving network interface.
The worst-case behavior is obtained when all the buffers in the switches
are full and when a packet of a flow loses arbitration with all other flows that
can contend with it. Let u
j
i
be the worst-case delay at switch j for a packet
of flow i, which needs to be computed. Let ts
1
and ts
2
be the injection and
ejection times at the end points of the network for flow i.Leth
i
be the total
number of hops in the path for flow i. Then, the worst-case latency for flow
is given by:
UB
i
= ts
1
+ ts
2
+
j
u
j
i
with j =0...h
i
(4.1)
A source node can have many flows, each to a different destination. In
practice, the cores should have support ...
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Publisher Resources

ISBN: 9781439841716