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Communication Architectures for Systems-on-Chip
book

Communication Architectures for Systems-on-Chip

by José L. Ayala
September 2018
Intermediate to advanced content levelIntermediate to advanced
449 pages
13h 16m
English
CRC Press
Content preview from Communication Architectures for Systems-on-Chip
174 Communication Architectures for SoC
5.4.2.3 Spacer Techniques
The spacer technique is based on the idea of transforming thin lateral di-
mensions, in the range of 10 to 100 nm, into vertical dimension by means of
anisotropic etch of the deposited materials. In [33], spacers with a thickness
of 40 nm were demonstrated with a line-width roughness of 4 nm and a low
variation across the wafer.
In [16], spacers were defined by means of low-pressure chemical vapor de-
position (LPCVD), then their number was duplicated by using the spacers
themselves as sacrificial layers for the following spacer set. This technique,
the iterative spacer technique (IST), yields silicon structures with sub-10 nm
width and a narrower half-pitch than the photolithography limit. ...
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Publisher Resources

ISBN: 9781439841716