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Communication Architectures for Systems-on-Chip
book

Communication Architectures for Systems-on-Chip

by José L. Ayala
September 2018
Intermediate to advanced content levelIntermediate to advanced
449 pages
13h 16m
English
CRC Press
Content preview from Communication Architectures for Systems-on-Chip
Hybrid Topology Exploration for RF-Based On-Chip Networks 211
Request
generation
1. Decoding
and routing
2.Arbitration
Grant
Selective
wakeup
Request
generation
Grant
Selective
wakeup
Bus
Transfer
Stages
Bus
Transfer
Stages
Packetization
Injection into
global router
Depacketiz-
ation
Grant
Selective
wakeup
Bus
Transfer
Stages
1. Decoding
and routing
2.Arbitration
1. Decoding
and routing
2.Arbitration
Local
Transaction
To global
network
From global
network
FIGURE 6.5
Hierarchical network packet traversal.
0
10
20
30
40
50
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
0.12
0.14
0.16
Avg packet latency(cycles)
Offered load (packets/node/cycle)
mesh cmesh
fbfly hier
FIGURE 6.6
Average pac ...
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Publisher Resources

ISBN: 9781439841716