Skip to Main Content
Communication Architectures for Systems-on-Chip
book

Communication Architectures for Systems-on-Chip

by José L. Ayala
September 2018
Intermediate to advanced content levelIntermediate to advanced
449 pages
13h 16m
English
CRC Press
Content preview from Communication Architectures for Systems-on-Chip
226 Communication Architectures for SoC
0
10
20
30
40
50
60
70
80
90
0.01
0.04
0.08
0.12
0.16
0.2
0.22
0.24
0.25
0.26
0.27
0.28
0.3
0.31
0.32
0.33
0.34
0.35
0.36
0.37
Network power consumption
Injection rate (packets/node/cycle)
UR mesh
UR meshRF-100%
UR meshRF-50%
EquiRFBW meshRF-100%
EquiRFBW meshRF-50%
EquiRFBW meshRF-25%
FIGURE 6.19
Network power consumption of Mesh+RF for UR traffic at 36 nodes.
0
10
20
30
40
50
60
70
80
90
100
Avg message latency
Injection rate
LC mesh
LC meshRF-100%
LC meshRF-50%
FIGURE 6.20
Average message latency of Mesh+RF for LC traffic at 36 nodes.
Hybrid Topology Exploration ...
Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Autonomic Networking-on-Chip

Autonomic Networking-on-Chip

Phan Cong-Vinh
On-Chip Communication Architectures

On-Chip Communication Architectures

Sudeep Pasricha, Nikil Dutt
Networks on Chips

Networks on Chips

Giovanni De Micheli, Luca Benini, Davide Bertozzi, Israel Cidon, Kees Goossens, Kwanho Kim, Kangmin Lee, Se-Joong Lee, Srinivasan Murali, Hoi-Jun Yoo

Publisher Resources

ISBN: 9781439841716