246 Communication Architectures for SoC
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[12] B. S. Feero and P. P. Pande. Networks-on-chip in a three-dimensional
environment: A performance evaluation. IEEE Trans. Comput., 58(1):32–
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[13] B. Grot, J. Hestness, S. W. Keckler, and O. Mutlu. Express cube topolo-
gies for on-chip interconnects. In High Performance Computer Architec-
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