348 Communication Architectures for SoC
The alternative to this approach is to build secure logic cells based on
existing standard cells. In this case, the design effort for new cell libraries is
minimal. This is the motivation for logic styles like WDDL [122] or MDPL [96].
Of course, each of the proposed logic styles also has other pros and cons
besides the design effort for the cells. Dual-rail precharge (DRP) logic styles
(e.g., SABL, TDPL, WDDL), which belong to the group of hiding logic styles,
are for example smaller than masked logic styles (e.g., MDPL, RSL, DRSL).
However, the security of DRP logic styles strongly depends on the balancing
of complementary wires in the circuit, while this is not the case for masked
logic styles. Design methods ...