
Security Issues in SoC Communication 353
2. Leakage caused by the difference of delay time between the input signals
of WDDL gates.
The impact of these leakages has been studied by Suzuki and Saeki [115].
The power consumption at the CMOS gate can be generally evaluated by:
P
total
= p
t
· C
L
· V
2
dd
· f
clk
+ p
t
· I
sc
· V
dd
· f
clk
+ I
leakage
· V
dd
(8.15)
where C
L
is the loading capacitance, f
clk
is the clock frequency, V
dd
is the
supply voltage, p
t
is the transition probability of the signal, I
sc
is the direct-
path short circuit current, and I
leakage
is the leakage current. As realized
from the formula 8.15, the power consumption at the first term is different
between the ...