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Communication Architectures for Systems-on-Chip
book

Communication Architectures for Systems-on-Chip

by José L. Ayala
September 2018
Intermediate to advanced content levelIntermediate to advanced
449 pages
13h 16m
English
CRC Press
Content preview from Communication Architectures for Systems-on-Chip
388 Communication Architectures for SoC
EM: Electromagnetic
EMA: Electromagnetic Analysis
EPDU: Evaluation-Precharge Detection Unit
FFT: Fast Fourier Transform
FIB: Focused Ion Beam
FPGA: Field Programmable Gate Array
FPRM: Fixed Polarity Reed-Muller canonical form
HW/SW: Hardware/Software
iMDPL: Improved Masked Dual-rail Precharge Logic
IPA: Inferential Power Analysis
LLVM: Low-Level Virtual Machine
MDPL: Masked Dual-rail Precharge Logic
PA: Power Analysis
PDA: Personal Digital Assistant
PDF: Probability Density Function
PMRML: Precharge Masked Reed-Muller Logic
QDI: Quasi-Delay Insensitive
RFID: Radio Frequency Identification Device
RIP: Randamized Initial Point
RNG: Random Number Generator
RPA: Refined Power Analysis
RSA: Rivest-Shamir-Adleman public key encryption ...
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Publisher Resources

ISBN: 9781439841716