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Computer Architecture, 5th Edition by David A. Patterson, John L. Hennessy

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C

Cache bandwidth
caches, 78
multibanked caches, 85–86
nonblocking caches, 83–85
pipelined cache access, 82
Cache block
AMD Opteron data cache, B-13, B-13 to B-14
cache coherence protocol, 357–358
compiler optimizations, 89–90
critical word first, 86–87
definition, B-2
directory-based cache coherence protocol, 382–386, 383
false sharing, 366
GPU comparisons, 329
inclusion, 397–398
memory block, B-61
miss categories, B-26
miss rate reduction, B-26 to B-28
scientific workloads on symmetric shared-memory multiprocessors, I-22, I-25, I-25
shared-memory multiprogramming workload, 375–377, 376
way prediction, 81
write invalidate protocol implementation, 356–357
write strategy, B-10

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