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Computer Architecture, 5th Edition by David A. Patterson, John L. Hennessy

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L

L1 caches See also First-level caches
address translation, B-46
Alpha 21164 hierarchy, 368
ARM Cortex-A8, 116, 116, 235
ARM Cortex-A8 vs. A9, 236
ARM Cortex-A8 example, 117
cache optimization, B-31 to B-33
case study examples, B-60, B-63 to B-64
directory-based coherence, 418
Fermi GPU, 306
hardware prefetching, 91
hit time/power reduction, 79–80
inclusion, 397–398, B-34 to B-35
Intel Core i7, 118–119, 121–122, 123, 124, 124, 239, 241
invalidate protocol, 355, 356–357
memory consistency, 392
memory hierarchy, B-39
miss rates, 376–377
multiprocessor cache coherence, 352
multiprogramming workload, 374
nonblocking cache, 85
NVIDIA GPU Memory, 304
Opteron memory, B-57
processor comparison, 242
speculative execution, 223 ...

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