T

Tag
AMD Opteron data cache, B-12 to B-14
ARM Cortex-A8, 115
cache optimization, 79–80
dynamic scheduling, 177
invalidate protocols, 357
memory hierarchy basics, 74
memory hierarchy basics, 77–78
virtual memory fast address translation, B-46
write strategy, B-10
Tag check (TC)
MIPS R4000, C-63
R4000 pipeline, B-62 to B-63
R4000 pipeline structure, C-63
write process, B-10
Tag fields
block identification, B-8
dynamic scheduling, 173, 175
Tail duplication, superblock scheduling, H-21
Tailgating, definition, G-20
Tandem Computers
cluster history, L-62, L-72
faults, D-14
overview, D-12 to D-13
Target address
branch hazards, C-21, C-42
branch penalty reduction, C-22 to C-23
branch-target buffer, 206
control flow instructions, ...

Get Computer Architecture, 5th Edition now with O’Reilly online learning.

O’Reilly members experience live online training, plus books, videos, and digital content from 200+ publishers.