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Computer Architecture and Organization

Book Description

The book uses microprocessors 8085 and above to explain the various concepts and provides additional information about the latest developments like Intel Core - II Duo, making it one of the most updated textbook in the market.

Table of Contents

  1. Computer Architecture and Organization (From 8085 to Core2Duo and beyond)
    1. Copyright
    2. Dedication (1/5)
    3. Dedication (2/5)
    4. Dedication (3/5)
    5. Dedication (4/5)
    6. Dedication (5/5)
    7. Preface
    8. Acknowledgements
    9. About the Author
    10. Chapter 1:Introduction
      1. 1.1 INTRODUCTION
      2. 1.2 HISTORICAL BACKGROUND
      3. 1.3 CLASSIFICATION
      4. SUMMARY
      5. POINTS TO REMEMBER
      6. QUICKSAND CORNER
      7. REVIEW QUESTIONS
    11. Chapter 2: Overview of Computer
      1. 2.1 BASIC STRUCTURE OF COMPUTER HARDWARE
      2. 2.2 FUNDAMENTAL UNITS
      3. 2.3 BASIC OPERATIONAL CONCEPTS
      4. 2.4 BUS STRUCTURE
      5. 2.5 BUILDING BLOCKS OF A COMPUTER
      6. SUMMARY
      7. POINTS TO REMEMBER
      8. QUICKSAND CORNER
      9. REVIEW QUESTIONS
    12. Chapter 3: Fundamentals of Digital Logic Circuits
      1. 3.1 INTRODUCTION
      2. 3.2 BOOLEAN ALGEBRA
      3. 3.3 LOGIC GATES
      4. 3.4 COMBINATIONAL CIRCUITS
      5. 3.5 ARITHMETIC CIRCUITS
      6. 3.6 SEQUENTIAL CIRCUITS
      7. 3.7 REGISTERS AND COUNTERS
      8. 3.8 MEMORY CIRCUITS
      9. 3.9 SOLVED EXAMPLES (1/2)
      10. 3.9 SOLVED EXAMPLES (2/2)
      11. SUMMARY
      12. POINTS TO REMEMBER
      13. QUICKSAND CORNER
      14. REVIEW QUESTIONS
    13. Chapter 4: Computer Arithmetic
      1. 4.1 INTRODUCTION
      2. 4.2 ADDITION AND SUBTRACTION
      3. 4.3 MULTIPLICATION ALGORITHMS
      4. 4.4 BOOTH'S ALGORITHM (1/2)
      5. 4.4 BOOTH'S ALGORITHM (2/2)
      6. 4.5 DIVISION ALGORITHMS
      7. 4.6 DIVISION OF SIGNED INTEGERS
      8. 4.7 FLOATING-POINT NUMBER REPRESENTATION (1/2)
      9. 4.7 FLOATING-POINT NUMBER REPRESENTATION (2/2)
      10. 4.8 FLOATING-POINT ARITHMETIC AND UNIT OPERATIONS
      11. 4.9 PIPELINED ALU
      12. SUMMARY
      13. POINTS TO REMEMBER
      14. QUICKSAND CORNER
      15. REVIEW QUESTIONS
    14. Chapter 5: Processor Basics
      1. 5.1 INTRODUCTION
      2. 5.2 PROCESSOR ARCHITECTURE AND ORGANIZATION
      3. 5.3 PROCESSOR OPERATION
      4. 5.4 REGISTER SET
      5. 5.5 STACK ORGANIZATION
      6. 5.6 INTERRUPTS
      7. 5.7 INTEL 8085 MICROPROCESSOR (1/2)
      8. 5.7 INTEL 8085 MICROPROCESSOR (2/2)
      9. 5.8 INTEL 8086 MICROPROCESSOR (1/3)
      10. 5.8 INTEL 8086 MICROPROCESSOR (2/3)
      11. 5.8 INTEL 8086 MICROPROCESSOR (3/3)
      12. 5.9 INTEL 8051 MICROCONTROLLER
      13. 5.10 RISC AND CISC PROCESSORS
      14. 5.11 INTEL 80386 PROCESSOR (1/2)
      15. 5.11 INTEL 80386 PROCESSOR (2/2)
      16. 5.12 INTEL PENTIUM 4 PROCESSOR (1/2)
      17. 5.12 INTEL PENTIUM 4 PROCESSOR (2/2)
      18. SUMMARY
      19. POINTS TO REMEMBER
      20. QUICKSAND CORNER
      21. REVIEW QUESTIONS
    15. Chapter 6: Instruction Set and Assembly Language Programming
      1. 6.1 INTRODUCTION
      2. 6.2 HIGH LEVEL, ASSEMBLY AND MACHINE LANGUAGE
      3. 6.3 FUNCTIONS AND CHARACTERISTICS OF INSTRUCTIONS
      4. 6.4 ADDRESSING MODES (1/2)
      5. 6.4 ADDRESSING MODES (2/2)
      6. 6.5 INSTRUCTION FORMATS AND FIELDS
      7. 6.6 8085 INSTRUCTION SET
      8. 6.7 8086 INSTRUCTION SET
      9. 6.8 8051 INSTRUCTION SET
      10. 6.9 ASSEMBLY LANGUAGE PROGRAMMING
      11. 6.10 ASSEMBLER
      12. 6.11 INTEL 80386 PROCESSOR
      13. 6.12 INTEL PENTIUM 4 PROCESSOR
      14. 6.13 SOLVED EXAMPLE
      15. SUMMARY
      16. POINTS TO REMEMBER
      17. QUICKSAND CORNER
      18. REVIEW QUESTIONS
    16. Chapter 7: The Memory System
      1. 7.1 INTRODUCTION
      2. 7.2 MEMORY CLASSIFICATION
      3. 7.3 MEMORY CHARACTERISTICS AND HIERARCHY
      4. 7.4 CACHE MEMORY (1/3)
      5. 7.4 CACHE MEMORY (2/3)
      6. 7.4 CACHE MEMORY (3/3)
      7. 7.5 MAIN MEMORY
      8. 7.6 SECONDARY MEMORY
      9. 7.7 VIRTUAL MEMORY
      10. 7.8 MEMORY MANAGEMENT
      11. 7.9 INTEL 80386 MEMORY ORGANIZATION
      12. 7.10 PENTIUM 4 MEMORY ORGANIZATION
      13. 7.11 MEMORY DECODING
      14. SUMMARY
      15. POINTS TO REMEMBER
      16. QUICKSAND CORNER
      17. REVIEW QUESTIONS
    17. Chapter 8: Input / Output Organization
      1. 8.1 INTRODUCTION
      2. 8.2 BASIC INPUT/OUTPUT STRUCTURE OF COMPUTERS
      3. 8.3 ASYNCHRONOUS DATA COMMUNICATION
      4. 8.4 SERIAL AND PARALLEL COMMUNICATIONS
      5. 8.5 PROGRAMMED I/O (POLLING)
      6. 8.6 INTERRUPT DRIVEN I/O
      7. 8.7 INTERRUPT CONTROLLER (8259)
      8. 8.8 DMA
      9. 8.9 DEVICE DRIVERS
      10. 8.10 STANDARD I/O INTERFACES (BUSES) (1/2)
      11. 8.10 STANDARD I/O INTERFACES (BUSES) (2/2)
      12. 8.11 BUS ARBITRATION
      13. 8.12 I/O PROCESSOR
      14. 8.13 SOLVED EXAMPLE
      15. SUMMARY
      16. POINTS TO REMEMBER
      17. QUICKSAND CORNER
      18. REVIEW QUESTIONS
    18. Chapter 9: Microprogramming and Microarchitecture
      1. 9.1 INTRODUCTION
      2. 9.2 PROBLEM OF ALLOWING DATA-FLOW (1/2)
      3. 9.2 PROBLEM OF ALLOWING DATA-FLOW (2/2)
      4. 9.3 INSTRUCTION CYCLES OF A PROCESSOR
      5. 9.4 HARDWIRED CONTROL
      6. 9.5 PROGRAMMED CONTROL
      7. 9.6 SEQUENCING AND EXECUTION OF MICROINSTRUCTIONS
      8. 9.7 SOLVED EXAMPLE
      9. 9.8 UTILIZING SYSTEM CLOCK
      10. 9.9 PROCESSOR DATA PATH DESIGN
      11. 9.10 SOLVED EXAMPLE
      12. SUMMARY
      13. POINTS TO REMEMBER
      14. QUICKSAND CORNER
      15. REVIEW QUESTIONS
    19. Chapter 10: Control Unit Operation
      1. 10.1 INTRODUCTION
      2. 10.2 CONTROL UNIT (CU)
      3. 10.3 MICRO-OPERATIONS (1/2)
      4. 10.3 MICRO-OPERATIONS (2/2)
      5. 10.4 CONTROL OF THE PROCESSOR
      6. 10.5 HARDWARE IMPLEMENTATION
      7. 10.6 SOLVED EXAMPLES (1/5)
      8. 10.6 SOLVED EXAMPLES (2/5)
      9. 10.6 SOLVED EXAMPLES (3/5)
      10. 10.6 SOLVED EXAMPLES (4/5)
      11. 10.6 SOLVED EXAMPLES (5/5)
      12. SUMMARY
      13. POINTS TO REMEMBER
      14. QUICKSAND CORNER
      15. REVIEW QUESTIONS
    20. Chapter 11: Operating System
      1. 11.1 INTRODUCTION
      2. 11.2 PROCESS AND ITS CONTROL
      3. 11.3 SCHEDULING ISSUES (1/2)
      4. 11.3 SCHEDULING ISSUES (2/2)
      5. 11.4 THREADS
      6. 11.5 SEMAPHORES
      7. 11.6 MEMORY MANAGEMENT ISSUES
      8. SUMMARY
      9. POINTS TO REMEMBER
      10. QUICKSAND CORNER
      11. REVIEW QUESTIONS
    21. Chapter 12: Pipelining
      1. 12.1 INTRODUCTION
      2. 12.2 SOME BASIC CONCEPTS
      3. 12.3 PIPELINE PERFORMANCE
      4. 12.4 DATA HAZARDS
      5. 12.5 INSTRUCTION HAZARDS
      6. 12.6 STRUCTURAL HAZARDS
      7. 12.7 CONTROLS AND DATA PATHS
      8. 12.8 PENTIUM 4 PIPELINE
      9. SUMMARY
      10. POINTS TO REMEMBER
      11. QUICKSAND CORNER
      12. REVIEW QUESTIONS
    22. Chapter 13: Parallel Processing and Super-Scalar Operation
      1. 13.1 INTRODUCTION
      2. 13.2 PARALLEL PROCESSING
      3. 13.3 NETWORK TOPOLOGIES (1/2)
      4. 13.3 NETWORK TOPOLOGIES (2/2)
      5. 13.4 PROGRAM PARALLELISM
      6. 13.5 SUPER-SCALAR OPERATION
      7. 13.6 ARRAY PROCESSOR
      8. 13.7 VECTOR PROCESSOR
      9. 13.8 FAULT TOLERANT COMPUTING
      10. SUMMARY
      11. POINTS TO REMEMBER
      12. QUICKSAND CORNER
      13. REVIEW QUESTIONS
    23. Chapter 14: Embedded Systems
      1. 14.1 INTRODUCTION
      2. 14.2 TYPES AND CLASSIFICATIONS
      3. 14.3 ARCHITECTURE OF MICROCONTROLLERS
      4. 14.4 ARCHITECTURE OF ATMEL AVR (1/2)
      5. 14.4 ARCHITECTURE OF ATMEL AVR (2/2)
      6. 14.5 ORGANIZATIONAL ISSUES
      7. 14.6 DESIGN ISSUES
      8. 14.7 EXAMPLE OF EMBEDDED SYSTEM
      9. SUMMARY
      10. POINTS TO REMEMBER
      11. QUICKSAND CORNER
      12. REVIEW QUESTIONS
    24. Chapter 15: Computer Peripherals
      1. 15.1 INTRODUCTION
      2. 15.2 KEYBOARD
      3. 15.3 MOUSE
      4. 15.4 PRINTERS
      5. 15.5 DISPLAY
      6. 15.6 TOUCH PADS
      7. SUMMARY
      8. POINTS TO REMEMBER
      9. QUICKSAND CORNER
      10. REVIEW QUESTIONS
    25. Appendix A: Number Systems
      1. A.1 INTRODUCTION
      2. A.2 DECIMAL NUMBERS
      3. A.3 BINARY NUMBERS
      4. A.4 HEXADECIMAL NUMBERS
      5. A.5 OCTAL NUMBERS
      6. A.6 CONVERSION TECHNIQUES
      7. SUMMARY
      8. POINTS TO REMEMBER
      9. REVIEW QUESTIONS
    26. Appendix B: SPARC and UltraSPARC
      1. B.1 INTRODUCTION
      2. B.2 BACKGROUND
      3. B.3 FUNCTIONAL OVERVIEW
      4. B.4 SPARC AND UltraSPARC REGISTER SET
      5. B.5 INTERNAL ARCHITECTURE
      6. B.6 PIPELINING
      7. B.7 INSTRUCTION FORMAT
      8. B.8 INSTRUCTION SET
      9. SUMMARY
      10. POINTS TO REMEMBER
      11. REVIEW QUESTIONS
    27. Appendix C: Power PC
      1. C.1 INTRODUCTION
      2. C.2 BACKGROUND
      3. C.3 INTERNAL ARCHITECTURE
      4. C.4 REGISTER SET OF POWER PC
      5. C.5 POWER PC INSTRUCTION SET
      6. C.6 PIPELINE OF POWER PC
      7. C.7 DATA TYPES OF POWER PC
      8. SUMMARY
      9. POINTS TO REMEMBER
      10. REVIEW QUESTIONS
    28. Appendix D: Intel Core2Duo
      1. D.1 DIFFERENCE BETWEEN DUAL CORE AND Core2Duo
      2. D.2 SALIENT FEATURES OF Core2Duo
      3. D.3 A FEW IMPORTANT SIGNALS
      4. D.4 LOW-POWER STATES AND POWER MANAGEMENT
      5. D.5 INTERNAL ARCHITECTURE
      6. D.6 INSTRUCTION SET (1/2)
      7. D.6 INSTRUCTION SET (2/2)
      8. SUMMARY
      9. POINTS TO REMEMBER
      10. REVIEW QUESTIONS
    29. Appendix E: MIPS R4000
      1. E.1 INTRODUCTION
      2. E.2 GENERAL ARCHITECTURE
      3. E.3 EXTERNAL SIGNALS
      4. E.4 INTERNAL ARCHITECTURE
      5. E.5 REGISTER SET
      6. E.6 MIPS R-SERIES INSTRUCTION SET
      7. E.7 INSTRUCTION FORMAT
      8. E.8 PIPELINE
      9. E.9 MEMORY MANAGEMENT
      10. E.10 EXCEPTION PROCESSING OF MIPS R4000
      11. SUMMARY
      12. POINTS TO REMEMBER
      13. REVIEW QUESTIONS
    30. Appendix F: Project Bank
      1. PART – A
      2. PART – B
      3. PART – C
    31. Answers for Target the Correct Option
    32. Glossary (1/2)
    33. Glossary (2/2)
    34. Acronyms
    35. Bibliography
    36. Index (1/2)
    37. Index (2/2)