388 Computer Architecture and Organization
Most modern processors have some hidden registers available to the processor only and by using
these registers in place of registers indicated by the program, speed of pipeline execution is enhanced.
This technique is known as register renaming. In the case of speculative execution, some instructions
are executed much before their real execution time, expecting that at a later stage these results would be
necessary for the pipeline.
Pentium 4 has a 20-stage pipeline and it decodes and translates all its CISC-like instructions to RISC-
like simple micro-codes and places within its trace-cache before placing within its pipeline. Because a
smaller number of microinstructions are involved, the execution speed is enhanced.
POINTS TO REMEMBER
R A pipelined processor stalls whenever any operation consumes more than its stipulated time-slice.
R Data hazards are primarily due to data dependency.
R Instruction hazards may be due to cache-miss or conditional branching instructions.
R Pipeline architecture demands additional data paths and data storage buffers for concurrent opera-
tions of different instructions during the same time-slice.
The basic aim of pipelined architecture is to speed
up the execution of instructions by concurrent
processing of different cycles related to it. Pipe-
line does not mean just to maintain an instruction
queue or fetching opcode during execution of the
previous opcode. It means a well-planned archi-
tecture and related organization for hazard-free
implementation of uninterrupted data ow, which
is the backbone of pipeline architecture.
Therefore, design of data paths and data stor-
age plays the critical role for it demanding maxi-
mum attention from its designers. Unless all these
are meticulously planned, the goal of implement-
ing pipeline technique may not be achieved.
Target the Correct Option
1. How many stages are there in the car-manu-
facturing assembly line shown in Figure 12.2 ?
(a) 3 (c) 5
(b) 4 (d) none of these
2. Ideally, the speed of instruction execution for
a two-stage pipelined processor in compari-
son with that of a similar processor but with-
out any pipeline is expected to be
(a) half (c) double
(b) same (d) none of these
3. A control-hazard may occur because of
(a) failure of a control signal
(b) non-availability of an instruction on time
(c) presence of multiple control signals
(d) none of these
4. The hazard due to data dependency may be
solved using hardware method by
(a) providing operand forwarding paths
between the result register and input reg-
isters of the ALU.
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