Instruction Set and Assembly Language Programming 155
AND Logically AND two operands
OR Logically OR two operands
XOR Logically XOR two operands
NOT Complement the operand
Shift right Shift operand right one bit. LSB is lost. New constant introduced at MSB.
Shift left Shift operand left one bit. MSB is lost. New constant introduced at LSB.
Rotate right Shift operand right one bit. LSB is shifted to MSB.
Rotate left Shift operand left one bit. MSB is shifted to LSB.
Compare Compare two operands and re ect the result through ags
Test Test ag bit(s)
Table 6.3 Common logical type instructions for processors
Branch unconditional Jump to the indicated address
Branch conditional Test condition and if condition is true then jump to indicated address
Call a subroutine Save PC on stack-top and branch to indicated address
Return from subroutine Reload PC by address saved on stack-top
Return from interrupt Enable interrupts and reload PC from stack-top
No operation Do nothing
Wait Wait for a signal input
Halt Stop functioning of the processor
Skip next instruction Execute the instruction immediately after the next instruction
Branch relative to PC Add PC with an offset and branch there
Table 6.4 Common program flow control type instructions for processors
6.4 ADDRESSING MODES
Addressing modes are generally related with data transfer type instructions and indicates the method by
which the data are targeted by the instruction. For example, we need to load a set of data in a register.
However, the concerned data might be a part of the instruction itself or it might be already available
at some external memory address or within an internal register of the processor. Depending upon the
method by which it is located, it would be the addressing mode of that instruction that loads that data
in the register. The following are some of the widely used addressing modes by different processors:
R Register direct
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156 Computer Architecture and Organization
R Register indirect
Brief discussions of these modes are presented below. Remember that all addressing modes are not
offered through all processors. Moreover, maximizing the number of addressing modes would make the
instruction decoding procedure of the processor more complex. It is on account of this reason for RISC
processors to offer lesser number of addressing modes.
In an immediate addressing mode, the target data are a part of the instruction. As it is so, to change the
data, the instruction itself has to be changed. That is the reason for which the immediate addressing
mode is referred to as loading a ‘ constant ’. Depending upon the processor, these data might be integers
(unsigned or signed) or real. An example of immediate addressing mode instruction for 8085 processor
LXI H, 1234H,
which loads the register pair HL by 16-bit data 1234H.
The student should note that addressing mode is not applicable for all instructions. For
example, the NOP (no operation) instruction can not have any addressing mode as it has noth-
ing to do with any data, either loading or storing it. Addressing modes are important for the
instruction set architecture level and particularly for instruction decoding. However, ‘every
instruction of a processor must be having an addressing mode’ is a false notion.
Figure 6.2 Example of immediate addressing mode
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