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Computer Arithmetic and Validity
book

Computer Arithmetic and Validity

by Ulrich Kulisch
April 2013
Intermediate to advanced content levelIntermediate to advanced
456 pages
16h 7m
English
De Gruyter
Content preview from Computer Arithmetic and Validity
Section 8.9 Top speed scalar product units 297
Figure 8.19. Block diagram of an SPU with short adder and local store for a 64 bit data word
and 128 bit data bus.
298 Chapter 8 Scalar products and complete arithmetic
cremented/decremented, a second set of flags is set up which is copied into the
flag word if a carry is generated. In Figure 8.19 two possible locations of the
summand after the shift are indicated. The carry word is always the most sig-
nificant word. Incrementing or decrementing this word never produces a carry.
Thus the adder/subtracter in ...
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Publisher Resources

ISBN: 9783110301731