
Switched-Capacitor Building Blocks
45
Comparing the preceding four equations with Equation (3.35), which describes an
ideal inverting analog integrator, we fi nd that the bilinear SC integrator has
introduced a gain nonlinearity error but no phase error, whereas the parallel SC
integrator has introduced both a gain nonlinearity error and a phase lag. These errors
are functions of wT and can be ignored when wT << 1. Given the same pole
frequency w
0
and clock sampling period T, the bilinear integrator’s magnitude gain is
approximately twice that of the parallel SC integrator (both are sampled at a low
frequency). However, given a fi xed T, as the ...