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Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits with Metamaterials by Yang Shang, Hao Yu

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150 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
reduced s ize and loss. In the following section, the feature of SEDFDA would
be revie wed first followed by detailed analys is for on-chip implementation
toward PA design.
7.3 PA Design with Power Combining Network
7.3.1 SEDFDA-Based PA Design
7.3.1.1 Review of SEDFDA
Wide ba ndwidth is usually achieved by distributed amplification in the mm-
wave region. One major limitation for traditional distributed PA is its low
PAE. As shown in Figure 7.2(a), each transistor outputs different power; there-
fore the transistors cannot be optimized simultaneously [7]. The power wasted
in the resistive terminations further degrades the efficiency. Both tra nsmission-
line and transistor sizes a re tapered in [7 ] to r ealize the maximized output
voltage swing at all distributed stage s (Figure 7.2(b)). Although each tran-
sistor still outputs different power, the same voltage swings are maintained
due to scaled transistor sizes. However, the large scaling ratio between transis-
tor stages limits the achievable number of distributed stage s and thus output
power. Furthermore, resistive terminations still c onsume power and degrade
efficiency. A new distributed amplifier called the dual-fed distributed ampli-
fier (DFDA) was pr oposed in [8], which can significantly improve the PAE
limitation for distributed PAs. As shown in Figure 7.2(c), the input signal is
split into 2 paths and fed into both ends of the gate line. The two outputs
from the drain line are then combined again as the output signal. It has been
proven that when a phase-shift of ±nπ (n=0,1,2...) is maintained between
transistors in both gate and drain lines, all transistors can see the same load,
and output the same power [200]. As a result, they can be optimized simul-
taneously. Moreover, the resistive terminations a re eliminated in DFDA, and
there is no additional power wasted. As a result, the PAE limitation of dis-
tributed PAs c an be resolved fundamentally. DFDA is further developed in
[9] as single-ended to eliminate the need of hybrid. The resulted topology is
shown in Figure 7.2(d), which is called the single-ended dual-fed distributed
amplifier (SEDFDA). Both input and output signals propagate to the open-
circuit ends and are reflected back. Since both forward and reflected signa ls
add up to each other under certain phase-shift of the T-line, the power gain
is further improved.
Note that both DFDA and SEDFDA require a phas e-shift of ±nπ
(n=0,1,2...) to be maintained between transistors in both gate and drain lines.
Since zero-phase-shift (n=0) is impossible to be realized by the traditional
T-line (which introduces phase-shift proportional to the T- line length), λ/ 2
T-line is used at PCB level to fulfill the phase-shift requirement, which is
however too bulky and lossy for on-chip implementation. One type of meta-
material called comp osite right/left-handed (CRLH) T-line can be used to
Power Combiner 151
(a)
(b)
(c)
(d)
Figure 7.2: Distributed amplifier (DA) topologies: (a) conventional
DA, (b) tapered DA [7], (c) DFDA [8], (d) SEDFDA [9].
realize a real zero-phase-shift, and is implemented for distributed amplifier
design in [200] and [201] at the PCB level for GHz region applications. How-
ever, at this frequency region, CRLH T-line is too bulky and lossy for on-chip
implementation in CMOS technology.
With frequency pushed into the mm-wave frequency region, such as 60GHz,
the lumped capacito r and inductor to build CRLH T-line structures are more
compact and less lossy and hence feasible for on-chip implementation in CMOS
technology. In this chapter, CRLH T-line-based ZPS is studied for the first
time in on-chip power amplifier desig n at 60GHz [202]. Detailed design consid-
erations are studied for ZPS to achieve low loss and wide-band performance
for 60GHz PA applications.
Both DFDA and SEDFDA have been analyzed in [200] and [203] but
targeted for PCB design at the GHz level, where T-lines are normally assumed
ideal. For on- chip power amplifier design at 60GHz and beyond, T-lines are
no longer ideal and the amplifier p erformance ca n be greatly affected. In the
following, we present the design analysis background of SEDFDA, and then
show the design implicatio ns when considering the non-ideal T-line targeted
for on-chip 60GHz applications.
7.3.1.2 SEDFDA Performance Analysis under Ideal T-Line Model
Figure 7.3 s hows the equivalent circuit for one N -stage SEDFDA. The upper
half is the gate line and the lowe r half the drain line. All parasitic components

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