176 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 7.25: Simulated and measured S parameters o f PA under 1.2
Notice the size of L
in the gate line is smaller than in the drain line due to
a larger parasitic capacitance at transistor gate.
The power combiner implemented in the 2
stage only has 2 branches,
mainly due to limitation of the tape-out area. More branches can be used to
enhance the p ower performance. Moreover, CPW transmiss ion lines are used
as parallel inductors for matching and DC biasing at the same time, therefore
no additional biasing circuit is required.
220.127.116.11 Simulation and Measurement Results
Circuit simulation is done in both Cadence and ADS. The chip is meas ured on
a CASCADE Microtech Elite-300 probe station and Agilent PNA-X (N5247A)
with frequency-sweep up to 11 0GHz. Me asurement for PA power performance
is done a t the center frequency (52GHz) with pads de-embedded.
Figure 7.25 shows the simulated and measured S parameters. An open-
short de -embedding was performed to obtain the results. From simulation,
the maximum gain is at 56.3 GHz with 11.3 dB. A 3-dB bandwidth of 2 1GHz
is achieved (40.3GHz ∼ 61.7GHz). At 60GHz, a 9.8- dB ga in is obtained. The
measured gain, on the other hand, has a peak value of 8.3 dB at 52 GHz. The
3-dB BW is 16GHz (44 to 60GHz). Compared with simulation, the center fre-