1.2. Few Pins = Massive Multiplexing

As shown in Figure 1.3, the 4-bit Intel 4004 microprocessor was packaged in a 14-pin dual-inline package (DIP). Consequently, this microprocessor’s 4-bit bus not only multiplexed access to the various components in the system, it also had to multiplex the bus-access addresses with the data on the same four wires. It took three clock cycles to pass a 12-bit address out over the bus and two or four more clock cycles to read back an 8- or 16-bit instruction. All instructions came from ROM in a 4004-based system. RAM accesses were even slower because they required one instruction to pass out the target address and then a second instruction to read data from or write data to the selected location. With a maximum ...

Get Designing SOCs with Configured Cores now with the O’Reilly learning platform.

O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.