O'Reilly logo

Designing SOCs with Configured Cores by Steve Leibson

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

1.7. I/O Bandwidth and Processor Core Clock Rate

This dichotomy is a significant point of difference between processor chips and processor cores. A processor core’s ability to support multiple simultaneous I/O transactions on several buses profoundly expands the possibilities for high-performance system architectures and topologies that would be uneconomical or impossible using packaged processor ICs for board-level system designs. Consequently, SOC designers should not feel the same pressures to pursue processors with high clock rates that PC designers use to achieve performance goals.

However, entrenched system-design habits and rules of thumb developed from the industry’s 35 years of collective, microprocessor-based, board-level system-design ...

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required