Once the abstracted system model produces the desired-performance results in system simulation, it’s time to expand the abstract computational and communication models into cycle-accurate ones. For processors, such models run the actual system firmware on a cycle-accurate instruction-set simulator (ISS). For RTL blocks, a cycle-accurate transaction-level model (TLM) is used. This simulation level provides a more detailed, less abstracted look at overall system performance and serves as a critical checkpoint in the system’s design. It validates the prior abstractions.