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Designing SOCs with Configured Cores by Steve Leibson

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4.10. Combining Instruction Extensions with Queues

The availability of queue interfaces tied directly to a processor’s execution units permits the use of Xtensa processors in an application domain previously reserved for hand-coded RTL logic blocks: flow-through processing. By combining input-and output-queue interfaces with designer-defined execution units, it’s possible to create a firmware-controlled processing block within a processor that can read values from input queues, perform a computation on those values, and output the result of that computation with a pipelined throughput of one clock per complete input-compute-output cycle.

Figure 4.7 illustrates a simple design of such a system with two 256-bit input queues, one 256-bit output ...

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