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Designing SOCs with Configured Cores by Steve Leibson

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5.16. MPSOC System-Level Simulation Example

Table 5.1 shows system-simulation results for a JPEG-encoding subsystem mapped onto a 5-processor MPSOC system. Two of the processors serve as the data source and data sink for the raw and JPEG images. Three processors are linked together in a dataflow style to form the example’s processing core. The JPEG-encoding algorithm was divided into three components: color conversion, DCT and quantization, and finally JPEG creation via Huffman encoding. Each processor has access to plentiful local and system-level memory resources. (These resources would be trimmed in a real system to the required sizes, as indicated by quantitative results from more detailed system simulations.) The table shows that the fast, ...

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