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Designing SOCs with Configured Cores by Steve Leibson

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5.17. SOC Design in the 21st Century

SOC complexity continues to grow in lockstep with Moore’s law. As the number of SOC blocks continues to increase, efficient interconnection of all system blocks and system-level modeling of the resulting complex systems become ever more important. Conventional on-chip interconnection schemes (namely buses and bus hierarchies) derived from board-level system designs of the 1970s and 1980s are increasingly unattractive for global on-chip interconnection because they incur severe routing liabilities and have significant speed limitations due to growing on-chip capacitance. In addition, available design tools from EDA vendors lack support for developing complex systems using multiple processors, and that situation ...

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