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Designing SOCs with Configured Cores by Steve Leibson

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5.4. Memory Caches

Xtensa and some Diamond Standard Series microprocessor cores use separate data and instruction memory caches to significantly improve processor performance. The data caches can be configured as a write-through or write-back cache. Cache locking allows cache lines to be fetched and locked down in the cache to avert cache misses during the execution of critical code.

The Xtensa ISA includes instructions that allow application code to manage and test the memory caches. These instructions allow the code to invalidate cache lines, directly read and write the cache arrays, and lock cache lines. Each cache way actually consists of two differently sized memory arrays: one array for data and one for the cache tag.

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