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Designing SOCs with Configured Cores by Steve Leibson

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5.5. Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF

Xtensa and some Diamond Standard Series microprocessor cores have dedicated RAM and ROM ports for local instruction and data memories. In addition, the Xtensa ISA includes an optional, configurable XLMI data port for high-speed connection to local memories and other device types. Local memories do not incur the same silicon overhead as a memory-cache way, because simple local memories (as opposed to caches) do not have tag arrays.

Each memory interface and the XLMI port have a busy signal that can be used to indicate that the associated memory is being used by some logic external to the processor (or that the memory is otherwise unavailable) and that the processor cannot immediately ...

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