Adversity is the diamond dust
Heaven polishes its jewels with.
With their configurability and extensibility, Tensilica’s 32-bit Xtensa microprocessor cores can perform a very wide array of SOC tasks. However, there are many on-chip tasks that do not require the processing and I/O bandwidths achievable with configurable Xtensa cores. Consequently, Tensilica has used the Xtensa ISA and the Xtensa Processor Generator to create architecturally compatible, pre-configured processor cores for specific task sets frequently encountered in SOC design.
These cores, comprising the Diamond Standard Series of pre-configured cores, offer a wide range of performance options ...