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Designing SOCs with Configured Cores by Steve Leibson

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6.11. Synchronization Instructions

All Diamond processor cores except the 232L implement the multiprocessor synchronization instructions listed in Table 6.8. These instructions can be used to implement communications structures such as semaphores between multiple tasks and multiple processors.

Table 6.8. MP synchronization instructions
Instruction mnemonicInstruction definition
L32AILoad with non-speculative characteristics. Forces all subsequent loads and stores to occur after completion of the L32AI instruction.
S32RIStore with non-speculative characteristics. Forces all previous stores to complete before initiation of S32RI-initiated store operation.
S32C1IAtomic conditional store used for updating synchronization variables in memory.

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