Designing SOCs with Configured Cores

7.6. Low-Power System Design and Operation

As gate counts soar into the hundreds of millions per chip, SOC power dissipation becomes an increasingly important design consideration for all systems. There are many ways to reduce system power. Some of these power-reducing methods relate to the processor’s design and are in the domain of the processor designer. Other methods are in the system designer’s domain.

A processor designer can reduce a processor’s power dissipation by minimizing clock activity inside of the processor through two techniques. The first technique is clock gating—switching off the clock to circuits that are not being exercised on a cycle-by-cycle basis. All Xtensa and Diamond processor cores including the Diamond 108Mini core ...